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高性能众核处理器申威26010 - 胡向东, 柯希明, 尹飞, 张新, 马永飞, 颜世云, 马超.pdf
147
11页
1次
2021-11-16
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DOI
:
issn
JournalofCom
p
uterResearchandDevelo
p
ment
(
):
,
 
稿
:
;
:
 
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ZX
)
Thisworkwassu
pp
ortedb
y
theNationalScienceandTechnolo
gy
Ma
j
orPro
j
ectsofHe
g
ao
j
i
(
ZX
)
 
 
 
 
 
 
 
 
 
(
 
 
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huxdismevi
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sinacom
)
Shenwei
:
A Hi
g
hPerformanceMan
y
CoreProcessor
HuXian
g
don
g
,
KeXimin
g
,
YinFei
,
ZhaoXin
,
MaYon
g
fei
,
YanShi
y
un
,
andMaChao
(
Shan
g
haiHi
g
hPer
f
ormanceInte
g
ratedCircuitDesi
g
nCenter
,
Shan
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hai
)
Abstract Basedonthemulticore
p
rocessorShenwei
,
thehi
g
h
p
erformanceman
y
core
p
rocessor
Shenweiado
p
tsSoC
(
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y
stemonchi
p
)
technolo
gy
,
andinte
g
ratescom
p
utin
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controlcoresand
com
p
utin
g
coresinasin
g
lechi
p
Itado
p
tsa6bitRISC
(
reducedinstructionsetcom
p
uter
)
instructionsetdesi
g
ned with an ori
g
inaldesi
g
n
,
andsu
pp
ortsbitSIMD
(
sin
g
leinstruction
multi
p
ledata
)
inte
g
erandfloatin
g
p
ointvectoraccelerationo
p
erationsIts
p
eak
p
erformancefor
double
p
recision floatin
g
p
oint o
p
erations reaches TFLOPSShenwei
p
rocessor is
manufacturedusin
g
nm
p
rocesstechnolo
gy
Thedieareaofthechi
p
ismorethanmm
,
andthe
coresofthechi
p
canrunstabl
y
withafre
q
uenc
y
ofGHzShenwei
p
rocessorado
p
tsa
variet
y
oflow
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owerconsum
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tiondesi
g
nsonthearchitecturelevel
,
themicroarchitecturelevel
,
and
thecircuitlevel
,
andthus
,
leadin
g
toa
p
eakener
gy
efficienc
y
ratioofGFLOPSWNotabl
y
,
boththeo
p
eratin
g
fre
q
uenc
y
andtheener
gy
efficienc
y
ratioofthechi
p
arehi
g
herthanthoseofthe
worldwidecontem
p
orar
yp
rocessor
p
roductsThrou
g
hthetechnicalinnovationsofhi
g
hfre
q
uenc
y
desi
g
n
,
stablereliabilit
y
desi
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y
ielddesi
g
n
,
Shenwei0haseffectivel
y
solvedtheissuesof
hi
g
hfre
q
uenc
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tar
g
et
,
p
owerconsum
p
tionwall
,
stabilit
y
andreliabilit
y
,
and
y
ield
,
allofwhichare
encounteredwhen
p
ursuin
g
the
g
oalofhi
g
h
p
erformancecom
p
utin
g
Ithasbeena
pp
liedsuccessfull
y
toaPFLOPSsu
p
ercom
p
uters
y
stemnamed
Sunwa
y
TaihuLi
g
ht
onalar
g
escale
,
andtherefore
,
canade
q
uatel
y
meetthecom
p
utin
g
re
q
uirementsforbothscientificanden
g
ineerin
g
a
pp
lications
Ke
y
words Shenweiinstructionset
;
com
p
utationcontrolcore
;
com
p
utin
g
core
;
low
p
owerdesi
g
n
;
ener
gy
efficienc
y
ration
 
 
,
(
s
y
stemonchi
p
,
SoC
)
,
,
RISC
(
reducedinstructionsetcom
p
uter
)
,
SIMD
(
sin
g
leinstructionmulti
p
ledata
)
,
TFLOPS
nm
,
die
mm
,
GHz
,
,
GFLOPSW
,
,
亿
􀅰
,
 
;
;
;
;
 TP
Fi
g
 TheoverallstructureofShenwei
 
  
CPU
(
central
p
rocessin
g
unit
)
,
,
,
CPU
[
]
,
CPU
亿
􀅰
,
,
,
,
,
,
亿
􀅰
,
To
p
,
􀅰
(
s
y
stemonchi
p
,
SoC
)
,
,
DDR
访
PCIE
IO
nm
,
亿
,
die
mm
,
GHz
,
TFLOPS
,
W
,
,
 
 
SoC
[
]
,
,
b
DDR
PCIE
IO
,
 
,
(
)
of 11
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